The present invention relates to a semiconductor memory device, and, more particularly, to a buffer for buffering an external clock in a memory device using a clock.
In low power memory devices, a scheme of turning off a clock buffer has been used for reduction of power consumption in a power-down mode and a self refresh mode. A conventional buffer and its peripheral control circuits will be described with reference to the drawings hereinafter.
FIG. 1 shows a conventional buffer and its peripheral circuits.
As shown in the drawing, the conventional buffer and its peripheral circuits include a clock enable buffer 110, a clock enable controller 120, a clock controller 130 and a clock buffer 140. The clock enable buffer 110 and the clock buffer 140 buffer a clock enable signal CKE and a clock CLK, respectively, and the clock buffer 140 is turned on or off by the control of its peripheral circuits, i.e., the clock enable controller 120 and the clock controller 130.
FIG. 2 is a detailed circuit diagram of the conventional clock buffer 140 shown in FIG. 1.
The conventional clock buffer 140 is provided with an inverter 141 composed of PMOS and NMOS transistors which take the external clock CLK via their gates, a PMOS transistor 142 and a NMOS transistor 143 for turning on or off the clock buffer 140 under the control of a clock buffer enable signal CLKBUF_EN, an inverter 144 for inverting and buffering an output of the inverter 141 to output a buffered clock CLKT, a delay line 145 for generation of a clock pulse CLKp4, two inverters 146 and 148, and a NAND gate 147.
In operation, the clock buffer 140 buffers an external clock CLK by the two inverters 141 and 144 connected in series, and delays and inverts the buffered clock CLKT by the delay line 145 and the inverter 146. Then, it NAND-operates the buffered clock and the clock CLKT from the inverter 144, and again inverts the NAND-operated result by the inverter 148 to output a clock pulse CLKp4. The PMOS and NMOS transistors 142 and 143, which take the clock buffer enable signal CLKBUF_EN via their respective gates, serve to turn off the clock buffer 140 when the clock buffer enable signal CLKBUF_EN of a low level is applied thereto.
FIG. 3 is a detailed circuit diagram of the conventional clock enable buffer 110 shown in FIG. 1.
The conventional clock enable buffer 110 is provided with two inverters 111 and 112 connected in series for buffering the clock enable signal CKE, an inverter 113 for inverting the buffered clock enable signal to provide an inverted clock enable signal CKEb, and a delay (setup hold delay) line 114 for delaying the buffered clock enable signal from the inverter 112 to output an internal clock enable signal CKET. The reason that delays the internal clock enable signal CKET by using the delay line 114 is to secure a setup hold time within the memory device.
FIG. 4 is a detailed circuit diagram of the conventional clock enable controller 120 shown in FIG. 1.
The conventional clock enable controller 120 is constituted by a first, a second and a third latch circuits 122 to 124, each having a corresponding one of pass gates PG1, PG2, and PG3 which are turned on or off by the clock CLKT buffered by the clock buffer 140.
In operation, the internal clock enable signal CKET is inverted by going through the inverter 121, and inverted and latched by the first latch circuit 122 at a falling edge of the clock CLKT buffered by the first pass gate PG1 which is turned on when a low signal is applied thereto. Further, the inverted and latched clock signal CKET is inverted and latched once again by the second latch circuit 123 at a rising edge following the falling edge of the clock CLKT buffered by the second pass gate PG2 which is turned on when a high signal is inputted thereto. Then, the signal latched by the second latch circuit 123 is inverted and latched once more at a falling edge following the rising edge of the clock CLKT buffered by the third pass gate PG3 which is turned on when a low signal is applied thereto. Lastly, the inverted and latched signal is inverted by an inverter 125 to output a delayed and inverted clock enable signal CKE_CLKb.
FIG. 5 depicts a detailed circuit diagram of the conventional clock controller 130 shown in FIG. 1.
The conventional clock controller 130 is constituted by a NOR gate 131, an inverter 132, and a NAND gate 133 which logically combine a LAS idle signal RASIDLE, a self refresh signal SREF, the inverted clock enable signal CKEb, and the delayed and inverted clock enable signal CKE_CLKb, to provide the clock buffer enable signal CLKBUF_EN.
In operation, when the LAS idle signal RASIDLE is a low level (i.e., active state) and the self refresh signal SREF is a low level (i.e., in case of no self refresh mode), an output of the NOR gate 131 becomes a high signal. Then, the high signal is inverted by the inverter 132 to apply a low signal to the NAND gate 133, and therefore, the clock buffer enable signal CLKBUF_EN outputted from the NAND gate 133 always becomes a high level. That is, the clock buffer 140 is always enabled.
Although any one of the LAS idle signal RASIDLE and the self refresh signal SREF is a high level, a high signal is applied to the NAND gate 133 and an output of the NAND gate 133 is decided by the control of the inverted clock enable signal CKEb and the delayed and inverted clock enable signal CKE_CLKb. In other words, the clock enable signal CLKBUF_EN becomes a low level only when the inverted clock enable signal CKEb and the delayed and inverted clock enable signal CKE_CLKb are all a high level, thereby turning off the clock buffer 140.
FIG. 6 is a timing chart describing the problems of the prior art.
As described above, in case of configuring the clock buffer 140 and the peripheral circuits 110 to 130, there occurs a failure or defect when the clock enable signal CKE is applied, in the state where the LAS idle signal RASIDLE is a high level, as depicted in the timing diagram. In the memory device, the state of the clock enable signal CKE at a rising edge of a (N−1)st clock defines the state of an Nth clock which is the following clock. As depicted in the timing diagram, therefore, if the clock enable signal CKE is a high level at a rising edge of a second clock 2CLK, the internal clock pulse CLKp4 is generated until a third clock 3CLK. And, the clock enable signal CKE is a high level at a rising edge of a fourth clock 4CLK, and thus, the clock pulse CLKp4 has to be generated at a fifth clock 5CLK. As shown in the timing diagram, however, the clock pulse CLKp4 which was not generated at the fourth clock 4CLK is generated and the clock pulse which should be generated at the fifth clock 5CLK is not generated.
The following are details of the above problems. First, in a standby state where the LAS idle signal RASIDLE is a high level, there occurs a failure or defect when the clock enable signal CKE falls to a low level at a high interval of the second clock 2CLK. Meanwhile, the clock buffer enable signal CLKBUF_EN is created by the NAND combination of the inverted clock enable signal CKEb and the delayed and inverted clock enable signal CKE_CLKb. Therefore, if the two inputs are all high level, the clock buffer enable signal CLKBUF_EN becomes disabled to a low level. Thus, the clock buffer enable signal CLKBUF_EN is a high level till the high interval of the second clock 2CLK, and therefore, the clock buffer enters a turn-on state, which generates the clock pulse CLKp4. When the clock enable signal CKE rises to a high level at a low interval of the third clock 3CLK, the inverted clock enable signal CKEb becomes a low level. Therefore, the clock buffer enable signal CLKBUF_EN KEb is a low level for a while and rises back to a high level. At the interval where the fourth clock 4CLK is a high level, when the clock enable signal CLK falls to a low level, the inverted clock enable signal CKEb becomes a high level. The falling of the fourth clock 4CLK does not happen yet, and thus, the delayed and inverted clock enable signal CKE_CLKb is a high level. Therefore, the clock buffer enable signal CLKBUF_EN becomes a low level again, and the internally buffered clock CLKT becomes a low level. At this time, the delayed and inverted clock enable signal CKE_CLKb becomes a low level again, and therefore, the clock buffer enable signal CLKBUF_EN becomes a high level again, thus turning on the clock buffer. The clock is at the high interval yet, and thus the buffered clock CLKT becomes a high level again. The clock buffer maintains the turn-on state until the falling of the fourth clock 4CLK. When the falling of the fourth 4CLK occurs, the delayed and inverted clock enable signal CKE_CLKb becomes a high level, thus turning off the buffer. Thus, there occurs a failure or defect in which the buffered clock CLKT of a high level is abnormally generated twice at the high interval of the fourth clock 4CLK, and the clock pulse CLKp4 that has to be generated is not generated in the fifth clock 5CLK.
In other words, in the standby state where the LAS idle signal RASIDLE is a high level, if the clock enable signal CKE falls to a logic low, the memory device enters into a power-down mode which makes the clock buffer turned off. In case where the clock enable signal CKE transits back to a high level to escape from the power-down mode, there takes place a failure or defect in which the clock pulse CLKp4 is not created in a specific condition. This problem is solved by a method which always turns on a small clock buffer introduced therein, in devices other than the low power memory device. However, it is not possible to realize the low power device using such a method of turning on the small clock buffer all the times.